The present disclosure relates in general to the non-destructive testing of performance degradation in electronic circuits and their components. More specifically, the present disclosure relates to systems and methodologies that efficiently and effectively isolate and distinguish hot carrier injection (HCI) degradation from bias temperature instability (BTI) degradation and other aging mechanisms using a disclosed stress-and-measure test sequence that synchronizes one or more ring oscillator circuits to a desired number of switching events independent of the stress protocol used to measure HCI degradation, and independent of the intrinsic frequency of each ring oscillator circuit.
Digital circuits in electronic systems such as computer processors, handheld electronic devices and digital cameras may include CMOS (complementary metal-oxide semiconductor) components such as n-channel field-effect-transistors (NFETs) and p-channel field-effect-transistors (PFETs) arranged in a complimentary fashion to perform logical functions. The electrical performance (e.g., operating speed, drive strength, etc.) of circuits that include NFET and PFET electronic components may change over time as a result of transistor aging mechanisms such as negative-bias temperature instability (NBTI), positive-bias temperature instability (PBTI) and hot-carrier injection (HCI). BTI degradation is a result of voltages applied to the FET gate, and HCI degradation occurs whenever the FET performs a switching operation. A general trend toward decreasing field-effect-transistor (FET) device geometries (e.g., gate length) has increased their vulnerability to aging mechanisms.
Test methodologies have been developed to measure or estimate the expected electrical performance degradation of FET circuit components when deployed in integrated circuits (ICs). Known testing methodologies use a stress-and-measure test sequence, wherein a stress related to a particular aging mechanism is applied to a circuit that includes FETs, and then performance characteristics of the FETs are measured and used to estimate and/or characterize the performance degradation that will result from the particular aging mechanism. Once characterized, the performance degradation of different implementations of the same general type of circuit may be compared in order to gain further insights on the expected impact of aging mechanisms on circuit performance.
A known stress-and-measure methodology to determine the rate of HCI degradation involves the use of a ring oscillator circuit. A typical ring oscillator circuit is formed from an odd number of inverters, NAND gates or equivalent logic elements (typically in the form of semiconductor devices) attached in a chain such that the output each logic element is fed to the input of the next logic element in the chain, and the last logic element is fed back to the first logic element to form a loop. The odd number of logic elements connected in series causes the ring oscillator output to oscillate between two voltage levels (e.g., an applied voltage potential and a ground potential) representing logical one (1) and logical zero (0). When used in a stress-and-measure testing configuration, a ring oscillator circuit may be subjected to an accelerating factor to accelerate a particular performance degradation, which can be measured, evaluated and compared with other ring oscillator circuits. For example, CMOS ICs experience HCI degradation whenever their semiconductor devices (e.g., FETs) experience switching events, and the switching event frequency depends on the applied stress voltage. The degradation is manifested in the decrease of the frequency of the ring oscillator. The degradation due to switching event frequency (i.e., HCI degradation) can be accelerated for purposes of testing by stressing the ring oscillator circuits with an accelerating factor such as the application of increasingly higher voltage stresses or the addition of increasingly greater loads between the ring oscillator stages.
Because ring oscillator circuits experience performance degradation from multiple aging mechanisms, it is important that the stress-and-measure sequence isolate and accurately analyze the performance degradation that results from a particular aging mechanism. For example, ring oscillator circuits experience both BTI degradation and HCI degradation. The above-described stress-and-measure sequences cannot distinguish HCI degradation from BTI degradation and other aging mechanisms. The type of logic element used to form the ring oscillator circuit also impacts the ring oscillator frequency. For example, a ring oscillator formed from NANDs has a different frequency than a ring oscillator formed from inverters. Because HCI degradation depends on the switching event frequency, a stress that distorts the intrinsic frequency can also distort the observed HCI degradation, which makes it difficult to directly compare the observed HCI degradation of two ring oscillator circuits that use, for example, different drive voltage levels in their stress-and-measure sequences, or that used different logic circuit configurations. Additionally, because the amount of BTI degradation in FETs depends on the duty cycle (i.e., on/off times) of the applied gate voltage, the isolation of HCI degradation from BTI degradation would be enhanced by using a stress-and-measure sequence that does not does not significantly impact the duty cycles of the various stress signals.
Accordingly, it would be beneficial to provide systems and methodologies that efficiently and effectively isolate HCI degradation from BTI degradation and other aging mechanisms independent of the stress protocol used to measure HCI degradation, and independent of the intrinsic frequency of each ring oscillator circuit.